This invention relates to digital memories; and more particularly, it relates to low-power high-speed high-density BiCMOS static memory chips.
BiCMOS memory chips are made partially of bipolar transistors and partially of CMOS transistors. Conventionally, on a BiCMOS memory chip, the CMOS transistors form thousands of memory cells, while the bipolar transistors receive and decode address input signals which select a particular cell. This is indicated in FIG. 1 wherein reference numeral 10 identifies one of the memory cells and reference numeral 20 identifies one address decoder which selects the memory cell 10.
Such a BiCMOS memory chip architecture is currently in wide use because it provides both a large number of cells and a fast operating speed. Other prior art memory chips which are made entirely of just CMOS transistors operate slower; while still other prior art memory chips which are made entirely of bipolar transistors provide fewer memory cells for any given chip size.
However, the bipolar address decoder 20 and the CMOS memory cell 10 in the FIG. 1 BiCMOS memory chip require different level digital signals in order to operate properly. Decoder 20 operates on "ECL" digital address signals while memory cell 10 operates digital "CMOS" signals. ECL signals have high and low levels that differ from each other by less than one volt, while "CMOS" signals which have high and low levels that differ from each other by at least three volts. For example, commonly used ECL high and low levels are -0.8 and -1.6 volts, and commonly used CMOS high and low levels commonly 0 and -5.2 volts.
Conventionally, to make the bipolar decoder operate with the CMOS memory cell, an ECL-to-CMOS voltage level translator 30 is disposed between them. Many examples of these voltage translator circuits as used in BiCMOS memory chips are described in the prior art.
For example, see FIG. 3 of a technical paper by Matsui et al entitled "An 8-ns 1-Mbit ECL BiCMOS SRAM with Double-Latch ECL-to-CMOS-Level Converters" in the IEEE Journal of solid state circuits, of Vol. 24, No. 5, October 1989, pages 1226-1231. See also FIG. 8 in a technical paper by Tamba et al entitled "An 8-ns 256K BiCMOS RAM" in the IEEE Journal of Solid State Circuits, Vol. 24, No. 4, August 1989, pages 1021-1026. See further FIG. 4 of a technical paper by Kertis et al entitled "A 12-ns ECL I/O 256 KX1-bit SRAM Using a 1-um BiCMOS Technology" in the IEEE Journal of Solid States Circuits, Vol. 23, No. 5, October 1988 pages 1048-1053.
However, all ECL-to-CMOS voltage level translators 30 add an inherent delay to the speed at which a memory cell can be addressed since the address signals pass through them. Also, all ECL-to-CMOS translators require a certain amount of chip space for their implementation, and that reduces the number of cells that can be placed on the chip. Further, all ECL-to-CMOS translators 30 dissipate some power, which in turn increases the amount of heat that must somehow be removed from the chip.
Accordingly, a primary object of the invention is to provide an improved architecture for a BiCMOS digital memory chip which operates without any ECL to CMOS translators and which therefore works faster while using less power and less chip space then the prior art.